1. Field of the Invention
The invention generally relates to the timing analysis of circuits, and, more particularly to systems and methods for analyzing the timing effects of spatial distribution in circuits.
2. Description of Related Art
In circuit design, one signal may need to arrive at a particular point in a circuit path before another signal. For example, a signal representing a stable data value may need to arrive at a memory element (e.g., a flip-flop or latch) before the clock signal that stores the value in the memory element. Alternatively, a signal representing a change in a data value may need to arrive at a memory element after the clock signal that stored the last data value. Two paths along which signals propagate so as to arrive at a particular pair of points (e.g., clock and data pins of a flip-flop) in a defined relationship with one another, as in the examples above, are often referred to as racing paths. Each set of racing paths typically includes an early path and a late path. The comparison of a pair of early and late mode signals to determine whether a particular requirement on their relative arrival times is called a timing test. An early mode signal or arrival time is the earliest time at which the value on a net or at a point can change from its previous cycle stable value, and a late mode signal or arrival time is the latest time at which the value on a net or at a point can settle to its final stable value for the current cycle.
Static timing analysis (STA) is a tool used for verification of circuit design and analysis of circuit performance. STA uses delay models to evaluate the delay in circuit paths. Most delay models used for STA employ parameter distributions, for example, parameter distributions for gate length, to define circuit performance. Each parameter distribution is a statistical measure that defines the possible values for each parameter and the relative likelihood of obtaining those values.
Three types of distributions are typically defined. The first type of distribution describes the variance of the chip means and defines possible mean values for a parameter that may be applied systematically across the chip. The second type of distribution describes a local mean that varies across the chip and defines the possible variation of the parameter across the chip. The third distribution is centered around the “local” mean and describes all the random, non-chip-dependent and non-position-dependent variations of the parameter.
In most cases, the three factors defined by the parameter distributions (mean or average value of a parameter, local variation of a parameter, and random variation of a parameter) are considered together, and an engineer designing a circuit considers the best-case and worst-case variation in a parameter. Typically, this would be done by performing an analysis in which a single value for each parameter is chosen from the chip mean distribution (e.g., the fastest for a “fast chip analysis” or the slowest for a “slow chip analysis”). Within this analysis early mode timing values are determined using the “best-case” (fastest) values within the local mean and random component distributions, and late mode timing values are determined using the “worst-case” (slowest) values within the local mean and random component distributions. Because the engineer considers the worst-case variation in the local mean of a parameter, pessimistic estimates of the delay in a circuit path are typically used (i.e., an unrealistically large difference between early and late mode timing values is used). Such pessimistic evaluations of the delay in circuit paths may lead to overdesigned circuits.